1. Field of the Invention
The present invention relates in general to the formatior of an integrated circuit including capacitors. In particular, the present invention relates to a method for forming a metal capacitor in a damascene process.
2. Description of the Related Art
Capacitors are deployed in various integrated circuits. For example, decoupling capacitors provide improved voltage regulation and noise immunity for power distribution. Capacitors also have wide applications in analog/logic, analog-to-digital, mixed signal, radio frequency circuit operations, and others.
A conventional method of manufacturing a semiconductor apparatus including a capacitor 20 that is formed of metal-insulator-metal layers is described with reference to FIGS. 1Axcx9c1D. As shown in FIG. 1A, an aluminum layer is deposited on an insulator 12 which contains interconnections and is formed on a silicon substrate having devices (not shown) thereon and therein. The aluminum layer is then patterned by masking and etching to form wires 14a and 14b. As shown in FIG. 1B, an insulator 16 with a tungsten plug 18 (hereafter xe2x80x9cW-plugxe2x80x9d) used to connect the aluminum wire 14a and the to-be-formed capacitor is formed on the aluminum wires 14a and 14b and the insulator 12. As shown in FIG. 1C, a first conductive plate 21, an insulator 22 and a second conductive plate 23 are sequentially deposited on the insulator 16 and the W-plug 18, and then patterned by masking and etching to obtain a capacitor 20. The first conductive plate 21, the lower electrode, is connected with the aluminum wire 14a through the W-plug 18. Another insulator 26 is deposited on the insulator 16 and the capacitor 20. The insulators 16 and 26 are patterned and W-plug 28a and W-plug 28b are formed therein. As shown in FIG. 1D, an aluminum layer is deposited on the insulator 26 and the W-plugs 28a and 28b. The aluminum layer is then patterned by masking and etching to form wires 34a and 34b. The aluminum wire 34a is connected with the second conductive plate 23 through the W-plug 28a. The aluminum wire 34b is connected with the aluminum wire 14b through the W-plug 28b. 
The above-mentioned traditional processes for integrating the capacitor 20 into an integrated circuit require several masking and etching steps to form the capacitor 20, which may increase overall fabrication costs.
As well, the aluminum used to fabricate the traditional interconnections cannot satisfy present-day requirements for enhanced integration and highly demanding speed of data transmission. Copper (Cu) has high electric conductivity tc reduce RC delay and can be substituted for the aluminum in the conducting wires. The use of copper in the conducting wires requires the use of processes, that is, damascene processes, because copper cannot be patterned by etching. This is because the boiling point of the copper chloride (CuCl2) produced by copper and the chlorine plasma usually used to etch metal is relatively high, about 1500xc2x0 C.
It is an object of the present invention to provide a method for forming a metal capacitor in a damascene process.
It is another object of the invention to reduce the number of masking and etching steps in manufacturing an integrated circuit including a capacitor.
Yet another object of the invention is to reduce the cost of manufacturing an integrated circuit including a capacitor.
Still another object of the invention is to provide easily controllable processes in manufacturing an integrated circuit including a capacitor.
Another object of the invention is to use the Cu processes to fabricate the integrated circuit including capacitors to reduce RC delay.
The present invention provides a method for forming a metal capacitor with a damascene process. Before fabricating the thin-film capacitor, a first Cu wire and a second Cu wire are prepared in a first insulator. A first sealing layer is formed on the first insulator and the first and second Cu wires. A second insulator and an anti-reflection layer are formed on the first sealing layer sequentially. The dual damascene structures including first and second Cu plugs and third and fourth Cu wires are formed in the anti-reflection layer, the second insulator and the first sealing layer, wherein the first Cu plug connects the third Cu wire and the first Cu wire, and the second Cu plug connects the fourth Cu wire and the second Cu wire. A third insulator and a metal layer are formed on the anti-reflection layer and the third and fourth Cu wires in turn. The metal layer and the third insulator are patterned by using the anti-reflection layer as an etching stop layer to form a upper electrode and a capacitor insulator corresponding to the third Cu wire. A fourth insulator is formed on the anti-reflector layer and the upper electrode. An additional dual damascene structures including third and fourth Cu plug and fifth and sixth Cu wires are formed in the fourth insulator, wherein the third Cu plug connects the fifth Cu wire and the upper electrode, and the fourth Cu plug connects the sixth Cu wire and the fourth Cu wire. A second sealing layer is formed, covering at least the fifth and sixth Cu wires.
The present invention provides another method for forming a metal capacitor with a damascene process. Before fabricating the thin-film capacitor, a first Cu wire and a second Cu wire are prepared in a first insulator. A first sealing layer is formed covering at least the first and second Cu wires. A second insulator and an anti-reflection layer are formed on the first sealing layer, sequentially. Dual damascene structures including first and second Cu plugs and third and fourth Cu wires are formed in the anti-reflection layer, the second insulator and the first sealing layer, wherein the first Cu plug connects the third Cu wire and the first Cu wire, and the second Cu plug connects the fourth Cu wire and the second Cu wire. A second sealing layer, a third insulator and a metal layer are formed on the anti-reflection layer and the third and fourth Cu wires sequentially. The metal layer and the third insulator are patterned using the second sealing layer as an etching stop layer to form a upper electrode and one part of a capacitor insulator corresponding to the third Cu wire, wherein the second sealing layer is the other part of the capacitor insulator. A fourth insulator is formed on the second sealing layer and the upper electrode. Additional dual damascene structures including third and fourth Cu plug and fifth and sixth Cu wires are formed in the fourth insulator and the second sealing layer, wherein the third Cu plug connects the fifth Cu wire and the upper electrode, and the fourth Cu plug connects the sixth Cu wire and the fourth Cu wire. A third sealing layer is formed at least on the fifth and sixth Cu wires.
These and other objects of the present invention will become readily apparent upon further review of the following specification and drawings.